Historically, traditional methods of testing printed circuit boards (PCBs) have required physical contact of an array of test probes with pins of integrated circuit packages (ICs) mounted on the boards. This array of test probes, called a "bed-of-nails," tests interconnections on a board between ICs by forcing an output pin on an IC to a test value and then sampling an input pin of a connected IC to see if it received the test value. Bed-of-nails can also test internal paths within an IC by forcing input pins to test values and sampling the results at output pins for comparison against ideal results.
However, the bed-of-nails approach does not work for surface mounted devices (SMDs) or VLSI circuits that have minimal spacing between pins. SMDs are mounted directly to the surface of the PCB and do not have pins that extend through the board for a probe to contact. Moreover, SMDs are often mounted on both sides of the board, further complicating testing of the IC. VLSI circuits can have as little as 15 thousandths of an inch between pins, making it virtually impossible to attach a probe to a pin.
In response to the need for an all-electronic approach to testing, the industry has developed a standard test architecture known informally as the JTAG standard and formally as the IEEE 1149.1 standard. This standard test architecture supports board-level testing using a bus that connects to boundary-scan test logic in each IC. The term "boundary scan" means that the input and output pins (I/O pins), or boundaries, of the IC may be stimulated/monitored electronically during a test. The test logic includes boundary scan registers for allowing test data to be electronically placed on an output pin or to be observed on an input pin without the need for physical contact by a probe. It also includes a test access port (TAP), within the IC which serves as an interface between test data registers (such as a boundary scan register) on the IC and the bus. However, the JTAG standard goes further. It includes permission for users to add and access other scan registers, or scan paths, within an IC to test the internal operation of the IC. This is a powerful option, since it addresses a common need to provide for the complete testing of integrated circuit embedded within an assembled electronic system.
The common approach for testing ICs that comply with the JTAG standard and provide access to internal scan paths is to temporarily substitute the JTAG test clock for the IC's normal system clock during testing of the internal scan path. The test clock "drives" the internal scan path during test and the system clock drives the scan path during normal operation. This switching between the two clocks is known as multiplexing and is easily done. However, there are several disadvantages to clock switching. First, the switching of clock signals raises risks of unreliable or false clocking and excessive clock slew, particularly for application-specific-integrated circuits (ASICs). Second, clock switching does not allow for "at-speed" testing. Instead, tests are executed at the test clock frequency, which is usually only a fraction of the system clock frequency in modern high-performance electronic systems. Unlike the system clock frequency, the test clock frequency is often constrained by such system-level concerns as high fan out clock distribution/skew and noise/susceptibility related to fast logic edge rates. And third, there is a growing demand, fueled by the advent of multi-chip module (MCM) technology, to test ICs at their maximum speeds before they are mounted in a module. Testing device limitations often make this testing of such ICs with the clock switching technique impractical.
An object of the invention, therefore, is to provide a method and apparatus for driving an internal scan path by a system clock during testing of the electronic system. Another object of the invention is to provide a flexible interface between JTAG or other test logic driven by a test clock and one or more internal scan paths driven by a system clock.